Optimal design for digital comparator using QCA nanotechnology with energy estimation

Abstract Quantum‐dot cellular automata (QCA) is a transistor‐less technology to implement the nanoscale circuit designs. QCA circuits are fast, highly dense and dissipate less energy as compared to widely used complementary metal oxide semiconductor (CMOS) technology. In this paper, a novel structure for digital comparator using QCA nanotechnology is proposed. Digital comparator is a basic and important module in central processing unit which compares two binary numbers. The proposed digital comparator is optimal, single layered with 0.50 clock latency and containing only 26 QCA cells. The proposed digital comparator is compared for the different performance metrics with the existing digital comparators. The calculations for energy dissipation are provided using QCA Designer‐E and QCA Pro tools. The proposed coplanar digital comparator is designed with minimum QCA cells which reduces the total cell area, total covered area and cost. Total cell area, total covered area and cost for the proposed digital comparator are 0.008 μm2, 0.023 μm2 and 0.006 respectively. Results show that energy dissipation for the proposed design is very less therefore, proposed digital comparator is energy efficient.