A Low Power and High Speed CMOS Comparator at Croyogenic Temperature

Cryogenic CMOS (Cryo-CMOS) circuits play an important role in quantum computer application. In readout circuit of quantum signal, Cryo-CMOS Analog to Digital Converter (ADC) is a very significant block. Comparator operated at cryogenic temperature becomes a required circuit. This work proposes a architecture of dynamic comparator based on Semiconductor Manufacturing International Corporation (SMIC) 0.18μm CMOS technology. This circuit has been simulated in BSIM3v3 model which was revised according to previous work. In 4.2K, the proposed comparator can achieve about 20% reduction of power compared to conventional double dynamic comparator.