2000•International Journal of ElectronicsRequires access
Design considerations for a high-speed CMOS comparator
Dagnachew Birru
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Abstract
Design considerations for a high-speed CMOS comparator for application in highspeed analogue-to-digital conversion are presented. Extensive simulations show that the comparator designed accordingly operates well above 250MHz clock speed in standard 0.5µm CMOS technology. An accuracy of 5mV and average power consumption of 0.3mW on 3.3V power supply is observed using simulations when it operates at 250MHz.