2005•Unpublished venueRequires access
0.8V 1GHz dynamic comparator in digital 90nm CMOS technology
Carsten Wulff, C. Ytterdal
Open publisher page 8 citations
Abstract
The design of a 0.8V 1GHz dynamic comparator in digital 90nm CMOS technology is presented. The work shows that low voltage, low power and high speed analog circuits are feasible in nano-scale CMOS technologies. The dynamic comparator dissipates a maximum of 222/spl mu/W at 1 GHz clock frequency with 100fF capacitive load and 0.8 V supply voltage. This is lower than comparable results.