Analysis and design of preamplifier-latch comparator for high accuracy switched-capacitor pipelined ADC

To be compatible with switched capacitor pipelined ADC,a CMOS preamplifier-latch comparator is designed and well analyzed for high speed,low kick-back noise and low mismatch offset.The cross-coupled load,capacitor neutralization and the optimizing ratio of PMOS/NMOS are adopted in the comparator.Since the proposed architecture is effective for achieving,the comparator has been used in high accuracy switched-capacitor pipelined ADC as Flash ADC.