Comparator Applicable for High Speed High Resolution ADC

A high speed high resolution clocked comparator circuit in CMOS technology is presented.The comparator includes a preamplifier,a dynamic latch and a clocked inverter.By applying the positive feed-back technique,a sufficient gain as well as speed of the preamplifier is achieved.The speed of the dynamic latch is improved by employing two cross-coupled latch and other feedback circuits.The comparator is designed and simulated in a 0.18μm 1.8V CMOS technology and the result shows that it meets the requirement of a 500 MSPS high resolution pipelined ADC.