CBSC pipelined ADC with comparator preset, and comparator delay compensation

We present a differential comparator-based switched-capacitor (CBSC) pipelined ADC with comparator preset, and comparator delay compensation. Compensating for the comparator delay by digitally adjusting the comparator threshold improves the ADC resolution 23 times. The ADC is manufactured in a 90 nm CMOS technology. The ADC core is 0.85 mm × 0.35 mm, with a 1.2 V supply for the core and 1.8 V for the input switches. The ADC has an effective number of bits (ENOB) of 7.05-bit, and a power dissipation of 8.5 mW at 60 MS/s.