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Charge Pump Design for Fast-locking PLL

Xiaozhi Liu

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Abstract

In this paper, the relationship between charge-pump phase-locked loop (CP-PLL) loop bandwidth and locking time is analyzed. By changing the operating mode of traditional charge pump, a PLL charge pump which can speed up locking process is proposed. The charge pump is composed of push-into-lock charge pump and keep-locking charge pump, whose operating mode is controlled by detecting the phase error in locking mode and locked mode. The proposed CP-PLL based on CSMC 0.5μm CMOS process had been simulated by Spectre. Final results confirm, the settling speed and locking speed of the improved CP-PLL is 2 times of the traditional one.

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What this paper is about

In this paper, the relationship between charge-pump phase-locked loop (CP-PLL) loop bandwidth and locking time is analyzed. By changing the operating mode of traditional charge pump, a PLL charge pump which can speed up locking process is proposed. The charge pump is composed of push-into-lock charge pump and keep-locking charge pump, whose operating mode is controlled by detecting the phase error in locking mode and locked mode. The proposed CP-PLL based on CSMC 0.5μm CMOS process had been simulated by Spectre. Final results confirm, the settling speed and locking speed of the improved CP-PLL is 2 times of the traditional one.

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Available abstract

In this paper, the relationship between charge-pump phase-locked loop (CP-PLL) loop bandwidth and locking time is analyzed. By changing the operating mode of traditional charge pump, a PLL charge pump which can speed up locking process is proposed. The charge pump is composed of push-into-lock charge pump and keep-locking charge pump, whose operating mode is controlled by detecting the phase error in locking mode and locked mode. The proposed CP-PLL based on CSMC 0.5μm CMOS process had been simulated by Spectre. Final results confirm, the settling speed and locking speed of the improved CP-PLL is 2 times of the traditional one.

Key concepts: Charge pump, Phase-locked loop, Settling time, Computer science, CMOS, PLL multibit, Charge (physics), Voltage

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