A Fast Locking Phase Locked Loop with Multiple Charge Pumps

A novel phase-locked loop(PLL) architecture with multiple charge pumps for fast locking has been proposed. The proposed PLL has three charge pumps. The effective capacitance and resistance of the loop filter can be scaled up/down according to the locking status by controlling the direction and magnitude of each charge pump current. The fast locking PLL that changes its loop bandwidth through controlling charge pumps depending on locking status has been designed. The capacitor usually occupying the larger portion of the chip is also minimized with the proposed scheme. Therefore, the PLL size of including resistors and capacitors at the bandwidth of 29.9KHz has been achieved. It has been fabricated with 3.3V CMOS process. The locking time is less than with the measured phase noise of -90.45dBc/Hz @1MHz at 851.2MHz output frequency.