Yang Ai-liang
Abstract
In this paper, the structure and design of RS decoder is described, and high-speed RS decoder has been implemented by using FPGA technology. The experimental results show that the max transfer rate is 100MB/s, and the decoder can meet these applications of high-code rate.
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In this paper, the structure and design of RS decoder is described, and high-speed RS decoder has been implemented by using FPGA technology. The experimental results show that the max transfer rate is 100MB/s, and the decoder can meet these applications of high-code rate.
Key concepts: Field-programmable gate array, Soft-decision decoder, Computer science, Code (set theory), Transfer (computing), Computer hardware, Embedded system, Decoding methods