ScholarLens Back to search
2006•Modern Electronics TechniqueRequires access

Design and FPGA Implementation of Reed-Solomon Encoder and Decoder

Zhiwen Pan

Open publisher page 0 citations

Abstract

Being an important linear block,the RS code,which has very strong capability of correcting random and burst errors,is widely used in various modern communication systems.This paper presents a RS decoder using Modified Euclidean Algorithm(MEA),and a new finitefield multiplier,which reduces the chip complexity of RS encoder and decoder,and discusses the design procedure of each blocks of (255,249) encoder and decoder in details.

About this research paper

What this paper is about

Being an important linear block,the RS code,which has very strong capability of correcting random and burst errors,is widely used in various modern communication systems.This paper presents a RS decoder using Modified Euclidean Algorithm(MEA),and a new finitefield multiplier,which reduces the chip complexity of RS encoder and decoder,and discusses the design procedure of each blocks of (255,249) encoder and decoder in details.

Why it matters

A significance statement is not available in the OpenAlex record.

Key contribution

A contribution statement is not available in the OpenAlex record.

Method / approach

Method details are not available in the OpenAlex metadata.

Main findings

Findings are not separately available in the OpenAlex metadata.

Limitations

Limitations are not available in the OpenAlex metadata.

Applications

Application details are not available in the OpenAlex metadata.

Available abstract

Being an important linear block,the RS code,which has very strong capability of correcting random and burst errors,is widely used in various modern communication systems.This paper presents a RS decoder using Modified Euclidean Algorithm(MEA),and a new finitefield multiplier,which reduces the chip complexity of RS encoder and decoder,and discusses the design procedure of each blocks of (255,249) encoder and decoder in details.

Key concepts: Encoder, Soft-decision decoder, Computer science, Field-programmable gate array, Reed–Solomon error correction, Computer hardware, Multiplier (economics), Decoding methods

Related papers

Related paper 1Related paper 2Related paper 3
Back to paper searchBrowse research topicsOriginal source
Design and FPGA Implementation of Reed-Solomon Encoder and Decoder — Research Paper | ScholarLens