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Principles and FPGA Implementation of RS Decoder Based on ME Algorithm

Zeng De-cai

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Abstract

RS(Reed-Solomon)code is a linear block code having very strong capability of correcting random and burst errors,which is widely used in various communication and memory systems.In this paper,the decoder is designed using modified Euclidean algorithm(MEA),the public extraction algorithm is used to optimize the muhi- plier,and the complexity and the power consumption of RS decoder are reduced by using the iteration and multiple methods.The all blocks of RS(255,239)decoder are realized by Verilog-HDL.

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What this paper is about

RS(Reed-Solomon)code is a linear block code having very strong capability of correcting random and burst errors,which is widely used in various communication and memory systems.In this paper,the decoder is designed using modified Euclidean algorithm(MEA),the public extraction algorithm is used to optimize the muhi- plier,and the complexity and the power consumption of RS decoder are reduced by using the iteration and multiple methods.The all blocks of RS(255,239)decoder are realized by Verilog-HDL.

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Available abstract

RS(Reed-Solomon)code is a linear block code having very strong capability of correcting random and burst errors,which is widely used in various communication and memory systems.In this paper,the decoder is designed using modified Euclidean algorithm(MEA),the public extraction algorithm is used to optimize the muhi- plier,and the complexity and the power consumption of RS decoder are reduced by using the iteration and multiple methods.The all blocks of RS(255,239)decoder are realized by Verilog-HDL.

Key concepts: Soft-decision decoder, Computer science, Verilog, Field-programmable gate array, Algorithm, Power consumption, Code (set theory), Euclidean algorithm

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