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FPGA Implementation of Viterbi Decoding Algorithm for Convolutional Codes

Huihong Liu

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Abstract

The FPGA implementation of Viterbi decoding algorithm for convolutional codes is presented The paper proposes some efficient methods to reduce the number of bits to represent the path metrics and the number of saving paths in the process of track back By using these methods,RAM size needed for saving metrics and paths and the power consumption are decreased, and the decoding speed is increased It is shown that the Viterbi algorithm of K =7 can be implemented with a single FPGA chip

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What this paper is about

The FPGA implementation of Viterbi decoding algorithm for convolutional codes is presented The paper proposes some efficient methods to reduce the number of bits to represent the path metrics and the number of saving paths in the process of track back By using these methods,RAM size needed for saving metrics and paths and the power consumption are decreased, and the decoding speed is increased It is shown that the Viterbi algorithm of K =7 can be implemented with a single FPGA chip

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Available abstract

The FPGA implementation of Viterbi decoding algorithm for convolutional codes is presented The paper proposes some efficient methods to reduce the number of bits to represent the path metrics and the number of saving paths in the process of track back By using these methods,RAM size needed for saving metrics and paths and the power consumption are decreased, and the decoding speed is increased It is shown that the Viterbi algorithm of K =7 can be implemented with a single FPGA chip

Key concepts: Computer science, Viterbi decoder, Viterbi algorithm, Convolutional code, Soft output Viterbi algorithm, Field-programmable gate array, Iterative Viterbi decoding, Decoding methods

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