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Implementation of Serial Viterbi Decoding Based on FPGA

Kuang Wang

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Abstract

Viterbi algorithm is applicable to decoding of convolutional codes. The hardware consumption of parallel Viterbi decoding shows exponential increase with the increase of constraint length of convolutional codes, which limits its hardware implementation. In this paper, the FPGA implementation of a serial Viterbi decoding architecture is presented. Suitable for decoding convolutional codes with long constraint length, this architecture saves hardware resource without performance deterioration.

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What this paper is about

Viterbi algorithm is applicable to decoding of convolutional codes. The hardware consumption of parallel Viterbi decoding shows exponential increase with the increase of constraint length of convolutional codes, which limits its hardware implementation. In this paper, the FPGA implementation of a serial Viterbi decoding architecture is presented. Suitable for decoding convolutional codes with long constraint length, this architecture saves hardware resource without performance deterioration.

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Available abstract

Viterbi algorithm is applicable to decoding of convolutional codes. The hardware consumption of parallel Viterbi decoding shows exponential increase with the increase of constraint length of convolutional codes, which limits its hardware implementation. In this paper, the FPGA implementation of a serial Viterbi decoding architecture is presented. Suitable for decoding convolutional codes with long constraint length, this architecture saves hardware resource without performance deterioration.

Key concepts: Computer science, Viterbi decoder, Convolutional code, Viterbi algorithm, Sequential decoding, Decoding methods, Field-programmable gate array, Iterative Viterbi decoding

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