A Implementation of a Non-backtracking Viterbi Decoding Algorithm in FPGA

Convolutional coding has been widely used in many communication fields,and Viterbi decoding algorithm is a maximum likelihood algorithm for the convolutional code.The hardware resource required for parallel Viterbi decoding shows an exponential increase with the increase of constraint length of convolutional code,which limits its hardware implementation.In this paper,a FPGA implementation of a serial Viterbi decoding architecture is presented,which saves hardware resource without performance deterioration.Meanwhile,a non-backtracking solution of Viterbi decoding algorithm using the RAM units of FPGA is provided in the paper.The solution can reduce the delay of decoding,and can be implemented in both serial decoding and parallel decoding.