Implementation of Parallel CRC Based on Verilog
Huang Chu-huang
Abstract
Huang Chu-huang
Abstract
In data communications,a high efficient error control method is needed to decrease the rate of error codes.Cyclic Redun-dancy Check(CRC) is widely used in data communications and measurement control fields as a powerful method for dealing with data errors.This paper presents a theoretical results in the context of realizing high speed hardware for parallel CRC.
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In data communications,a high efficient error control method is needed to decrease the rate of error codes.Cyclic Redun-dancy Check(CRC) is widely used in data communications and measurement control fields as a powerful method for dealing with data errors.This paper presents a theoretical results in the context of realizing high speed hardware for parallel CRC.
Key concepts: Computer science, Verilog, Error detection and correction, Context (archaeology), Cyclic redundancy check, Control (management), Word error rate, Parallel computing