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Applicating Research of CRC Parallel Algorithm Based on FPGA

Jian Hu

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Abstract

Cyclic Redundancy Check(CRC) algorithm is widely used in communication fields to improve the reliability for data transmission.According to the CRC checksum principle that commonly used in the communication process,this paper introduce the principle of CRC calculation.After having analyzed the classical CRC algorithm implementation process,this article introduces a fast parallel CRC calculation based on FPGA.The QuartusII8.0 of Altera Inc is chosen as a compiler,simulation platform,the modeling and realization is performed by taking use of VHDL,and the simulation and verification is achieved in Quartus II software platform.The algorithm achieves a higher processing speed and better stability in actual applications.

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What this paper is about

Cyclic Redundancy Check(CRC) algorithm is widely used in communication fields to improve the reliability for data transmission.According to the CRC checksum principle that commonly used in the communication process,this paper introduce the principle of CRC calculation.After having analyzed the classical CRC algorithm implementation process,this article introduces a fast parallel CRC calculation based on FPGA.The QuartusII8.0 of Altera Inc is chosen as a compiler,simulation platform,the modeling and realization is performed by taking use of VHDL,and the simulation and verification is achieved in Quartus II software platform.The algorithm achieves a higher processing speed and better stability in actual applications.

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Available abstract

Cyclic Redundancy Check(CRC) algorithm is widely used in communication fields to improve the reliability for data transmission.According to the CRC checksum principle that commonly used in the communication process,this paper introduce the principle of CRC calculation.After having analyzed the classical CRC algorithm implementation process,this article introduces a fast parallel CRC calculation based on FPGA.The QuartusII8.0 of Altera Inc is chosen as a compiler,simulation platform,the modeling and realization is performed by taking use of VHDL,and the simulation and verification is achieved in Quartus II software platform.The algorithm achieves a higher processing speed and better stability in actual applications.

Key concepts: Computer science, Cyclic redundancy check, VHDL, Field-programmable gate array, Checksum, Algorithm, Redundancy (engineering), Compiler

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