Implementation of CRC Based on FPGA

This paper introduces the algorithm,theory and checking regulations of CRC,analyzes the computational process of CRC,takes CRC-16 as an example and gives some of the source program of hardware description language Verilog HDL to achieve CRC-16.It is not only the generator of check codes but also the parity checker of data waiting for checking.This paper gives the result of emulation and synthesis of the example,which can be realized in field programmable gate array(FPGA) with a work frequency up to 400 MHz.