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A Low Complexity Reed-Solomon Decoder for DVB System

Hao Min

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Abstract

A low complexity VLSI implementation of Reed-Solomon decoder for DVB(Digital Video Broadcasting) system is presented.The advantage of high rate clock in the DVB system results in a higher decode speed in the Modified Euclidean algorithm block,optimization of the pipeline structure of the decoder and efficient reduction of the chip area.The RS decoder has been synthesized with SMIC 0.25 μm technology and the implementation result shows a scale of about(31 000) gates.

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What this paper is about

A low complexity VLSI implementation of Reed-Solomon decoder for DVB(Digital Video Broadcasting) system is presented.The advantage of high rate clock in the DVB system results in a higher decode speed in the Modified Euclidean algorithm block,optimization of the pipeline structure of the decoder and efficient reduction of the chip area.The RS decoder has been synthesized with SMIC 0.25 μm technology and the implementation result shows a scale of about(31 000) gates.

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Available abstract

A low complexity VLSI implementation of Reed-Solomon decoder for DVB(Digital Video Broadcasting) system is presented.The advantage of high rate clock in the DVB system results in a higher decode speed in the Modified Euclidean algorithm block,optimization of the pipeline structure of the decoder and efficient reduction of the chip area.The RS decoder has been synthesized with SMIC 0.25 μm technology and the implementation result shows a scale of about(31 000) gates.

Key concepts: Digital Video Broadcasting, Computer science, Soft-decision decoder, Video decoder, Pipeline (software), Very-large-scale integration, Clock rate, Reduction (mathematics)

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