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VLSI design of Reed-Solomon decoder based on new architecture of modified Euclidean algorithm

Xiaoyang Zeng, Zhenyu Gu, Chao Chen, Qianling Zhang

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Abstract

A RS(255, 223) decoder based on modified Euclidean (mE) algorithm is implemented. A new VLSI architecture of the error-locator and error-evaluator module for mE algorithm is studied. The new architecture can reduce the complexity of the module and the error-probability of the decoder is cut-down also. The RS decoder is implemented using 0.35 mm CMOS technology, and the chip-area is about 30,000 gates, system clock is 65MHz, throughout is about 500Mbits/s. The decoder has the merits of low latency, low complexity and moderate throughput of data.

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What this paper is about

A RS(255, 223) decoder based on modified Euclidean (mE) algorithm is implemented. A new VLSI architecture of the error-locator and error-evaluator module for mE algorithm is studied. The new architecture can reduce the complexity of the module and the error-probability of the decoder is cut-down also. The RS decoder is implemented using 0.35 mm CMOS technology, and the chip-area is about 30,000 gates, system clock is 65MHz, throughout is about 500Mbits/s. The decoder has the merits of low latency, low complexity and moderate throughput of data.

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Available abstract

A RS(255, 223) decoder based on modified Euclidean (mE) algorithm is implemented. A new VLSI architecture of the error-locator and error-evaluator module for mE algorithm is studied. The new architecture can reduce the complexity of the module and the error-probability of the decoder is cut-down also. The RS decoder is implemented using 0.35 mm CMOS technology, and the chip-area is about 30,000 gates, system clock is 65MHz, throughout is about 500Mbits/s. The decoder has the merits of low latency, low complexity and moderate throughput of data.

Key concepts: Very-large-scale integration, Soft-decision decoder, Computer science, Euclidean algorithm, CMOS, Latency (audio), Architecture, Decoding methods

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