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A low-complexity, high-speed Reed-Solomon decoder [fiber-optic communication system applications]

H. Lee, Akbar Azam

Open publisher page 1 citations

Abstract

This paper presents a low-complexity, high-speed RS(255,239) decoder architecture, using a modified Euclidean (ME) algorithm, for high-speed fiber optic communication systems. The RS decoder features a low-complexity key equation solver using a novel pipelined recursive ME algorithm block. Pipelining allows inputs to be received at very high fiber optic rates and outputs to be delivered at correspondingly high rates with minimum delay. The recursive structure enables us to implement the low-complexity ME algorithm block. The low-complexity, high-speed RS decoder has been designed and implemented with 0.13 /spl mu/m CMOS technology at a supply voltage of 1.1 V. It is suggested that the proposed RS decoder operates at a clock rate of 770 MHz and has a throughput of 6.16 Gb/s.

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What this paper is about

This paper presents a low-complexity, high-speed RS(255,239) decoder architecture, using a modified Euclidean (ME) algorithm, for high-speed fiber optic communication systems. The RS decoder features a low-complexity key equation solver using a novel pipelined recursive ME algorithm block. Pipelining allows inputs to be received at very high fiber optic rates and outputs to be delivered at correspondingly high rates with minimum delay. The recursive structure enables us to implement the low-complexity ME algorithm block. The low-complexity, high-speed RS decoder has been designed and implemented with 0.13 /spl mu/m CMOS technology at a supply voltage of 1.1 V. It is suggested that the proposed RS decoder operates at a clock rate of 770 MHz and has a throughput of 6.16 Gb/s.

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Available abstract

This paper presents a low-complexity, high-speed RS(255,239) decoder architecture, using a modified Euclidean (ME) algorithm, for high-speed fiber optic communication systems. The RS decoder features a low-complexity key equation solver using a novel pipelined recursive ME algorithm block. Pipelining allows inputs to be received at very high fiber optic rates and outputs to be delivered at correspondingly high rates with minimum delay. The recursive structure enables us to implement the low-complexity ME algorithm block. The low-complexity, high-speed RS decoder has been designed and implemented with 0.13 /spl mu/m CMOS technology at a supply voltage of 1.1 V. It is suggested that the proposed RS decoder operates at a clock rate of 770 MHz and has a throughput of 6.16 Gb/s.

Key concepts: Computer science, Block (permutation group theory), Clock rate, Decoding methods, Computational complexity theory, Soft-decision decoder, Communication complexity, Parallel computing

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