2009Telecom Power TechnologyRequires access

Design of All Digital Phase-Locked Loop

Yang Hong

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Abstract

All Digital Phase-Locked Loop(ADPLL) is generally used in digital communication field.In this paper,a method that realizes all digital phase-locked loop by Verilog hardware description language is presented.First,the structure of ADPLL is described in detail.The working principle of each module is analyzed.On the basis of theoretical analysis,first order all digital phase-locked loop mathematical model is established.Then,the simulation results of some Verilog code and circuit design are given.According to the simulation results,performance of the phase-lock loop system is analyzed briefly.

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What this paper is about

All Digital Phase-Locked Loop(ADPLL) is generally used in digital communication field.In this paper,a method that realizes all digital phase-locked loop by Verilog hardware description language is presented.First,the structure of ADPLL is described in detail.The working principle of each module is analyzed.On the basis of theoretical analysis,first order all digital phase-locked loop mathematical model is established.Then,the simulation results of some Verilog code and circuit design are given.According to the simulation results,performance of the phase-lock loop system is analyzed briefly.

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Available abstract

All Digital Phase-Locked Loop(ADPLL) is generally used in digital communication field.In this paper,a method that realizes all digital phase-locked loop by Verilog hardware description language is presented.First,the structure of ADPLL is described in detail.The working principle of each module is analyzed.On the basis of theoretical analysis,first order all digital phase-locked loop mathematical model is established.Then,the simulation results of some Verilog code and circuit design are given.According to the simulation results,performance of the phase-lock loop system is analyzed briefly.

Key concepts: Phase-locked loop, Loop (graph theory), Lock (firearm), Verilog, Computer science, Delay-locked loop, Electronic engineering, Hardware description language

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