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2008•Modern Electronics TechniqueRequires access

Design and Analysis of All Digital Phase-Locked Loop

PU Xiaoting

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Abstract

A way of designing a first-order All Digital Phase-Locked Loop(ADPLL) using FPGA is presented in this brief.First,it describes the structure of ADPLL particularly,analyzes the theory.Then it designs the modules using VHDL and drew the time order graph for every module.Finally it finds first-order mathmatic module of ADPLL.The simulation test proves the feasibility for the ADPLL.The result is mainly in accordance with the analysis of theory.

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What this paper is about

A way of designing a first-order All Digital Phase-Locked Loop(ADPLL) using FPGA is presented in this brief.First,it describes the structure of ADPLL particularly,analyzes the theory.Then it designs the modules using VHDL and drew the time order graph for every module.Finally it finds first-order mathmatic module of ADPLL.The simulation test proves the feasibility for the ADPLL.The result is mainly in accordance with the analysis of theory.

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Available abstract

A way of designing a first-order All Digital Phase-Locked Loop(ADPLL) using FPGA is presented in this brief.First,it describes the structure of ADPLL particularly,analyzes the theory.Then it designs the modules using VHDL and drew the time order graph for every module.Finally it finds first-order mathmatic module of ADPLL.The simulation test proves the feasibility for the ADPLL.The result is mainly in accordance with the analysis of theory.

Key concepts: VHDL, Phase-locked loop, Field-programmable gate array, Computer science, Loop (graph theory), Electronic engineering, Embedded system, Engineering

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