Xia Zhang
Abstract
The system structure and the principle of ADPLL is introduced.A design way of all digital phase locked loop that will increase synchronous range based on PFGA is proposed in detail,and the partial verilog HDL code and simulation wave-form is given.
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The system structure and the principle of ADPLL is introduced.A design way of all digital phase locked loop that will increase synchronous range based on PFGA is proposed in detail,and the partial verilog HDL code and simulation wave-form is given.
Key concepts: Phase-locked loop, Field-programmable gate array, Verilog, Loop (graph theory), Code (set theory), Computer science, Phase (matter), Range (aeronautics)