Implementation of Cyclic Redundancy Check Algorithm Based on FPGA

Cyclic Redundancy Check(CRC) is an error_detection code widely used in the digital communication. Based on the principle of CRC,taking the ordinary CRC-16 as an example,the CRC algorithm is designed by the hardware description language Verilog HDL.The simulation waveform and the encode module for share are also given under Quartus II 6.0,an EDA tool developed by Altera Company.The module is not only the generator of CRC but also the checker of data waiting for checking.The simulation has shown that the method is effective,and it’s working frequency is up to 420.17 MHz.