Implementation of cyclic redundancy check algorithm using FPGA with high speed

Cyclic Redundancy Check(CRC) is a type of channel coding technology used for error detection and control in digital communication.After introducing the principle of CRC,taking CRC-16 polynomial as an example,the author described the CRC algorithm using hardware description language Verilog HDL.CRC module is synthesized,fitted and simulated by Quartus II 8.0,programmed into the Cyclone II family device EP2C35F672C6 and implemented on DE2 board.The module is the combination of CRC generator and CRC checker.In addition to,this CRC module can be packed as a custom component with Avalon-MM interface and be shared with other designer.The result of the experiment showed that this CRC module has a high speed,less resources consumption,and it is used in actual application.