Design of a Synthesizable Finite State Machine Based on Verilog HDL

Verilog HDL is a hardware description language,which can describe hardware not only at gate level and register transfer level but also at algorithmic level.Finite state machine(FSM) is an important part of a digital system.This paper studies different coding styles and describing methods for designing FSM using Verilog HDL.It introduces synthesis principles of FSM as well.Furthermore,a RAM controller is presented as a FSM design example.The synthesis and simulation of the design are implemented separately through Synplify Pro and Quartus II.