Design of high-speed and synthesizable finite state machine based on Verilog HDL

FSM(Finite State Machine) is widely used in the controller design of digital system.Synthesizable state machine design using Verilog has many coding styles that normally generate combinational logic outputs.Timing analysis shows that state machine with combinational outputs is not well suited for high-speed system.A state machine with registered output is presented,which is suited for high-speed system.Finally,a method of state encoding for registering the FSM outputs and synthesizable Verilog coding style is provided with an example.