ScholarLens Back to search
2009•Microcomputer applicationsRequires access

Design of Digital Phase-Locked Loop Based on FPGA

Lirong Yang

Open publisher page 0 citations

Abstract

Digital phase-locked Loop(DPLL)technology will be used widely.This paper has proposed a methodology of designing DPLL,systematically states its operational principle which is followed by the designing processes and simulating results of the main modules.This methodology,based on VHDL technique,can be implemented by field programmable logic array(FPGA).

About this research paper

What this paper is about

Digital phase-locked Loop(DPLL)technology will be used widely.This paper has proposed a methodology of designing DPLL,systematically states its operational principle which is followed by the designing processes and simulating results of the main modules.This methodology,based on VHDL technique,can be implemented by field programmable logic array(FPGA).

Why it matters

A significance statement is not available in the OpenAlex record.

Key contribution

A contribution statement is not available in the OpenAlex record.

Method / approach

Method details are not available in the OpenAlex metadata.

Main findings

Findings are not separately available in the OpenAlex metadata.

Limitations

Limitations are not available in the OpenAlex metadata.

Applications

Application details are not available in the OpenAlex metadata.

Available abstract

Digital phase-locked Loop(DPLL)technology will be used widely.This paper has proposed a methodology of designing DPLL,systematically states its operational principle which is followed by the designing processes and simulating results of the main modules.This methodology,based on VHDL technique,can be implemented by field programmable logic array(FPGA).

Key concepts: DPLL algorithm, VHDL, Field-programmable gate array, Computer science, Phase-locked loop, Loop (graph theory), Gate array, Computer hardware

Related papers

Related paper 1Related paper 2Related paper 3
Back to paper searchBrowse research topicsOriginal source
Design of Digital Phase-Locked Loop Based on FPGA — Research Paper | ScholarLens