2005Journal of Changchun Institute of TechnologyRequires access

Design of all digital phase locked loop based on VHDL

NI Hong-xia

Open publisher page 1 citations

Abstract

In this paper,the operation principle of digital phase locked loop(DPLL) is introduced.A method for designing DPLL is proposed based on VHDL technique,and realized with complex programmable logic device(CPLD).The designing processes and the simulating results of the main modules are given.

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What this paper is about

In this paper,the operation principle of digital phase locked loop(DPLL) is introduced.A method for designing DPLL is proposed based on VHDL technique,and realized with complex programmable logic device(CPLD).The designing processes and the simulating results of the main modules are given.

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Available abstract

In this paper,the operation principle of digital phase locked loop(DPLL) is introduced.A method for designing DPLL is proposed based on VHDL technique,and realized with complex programmable logic device(CPLD).The designing processes and the simulating results of the main modules are given.

Key concepts: DPLL algorithm, VHDL, Phase-locked loop, Complex programmable logic device, Computer science, Programmable logic device, Loop (graph theory), Electronic engineering

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