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Low-Power LVDS Receiver with Equalization for 8B/10B SerDes

You Liang Yang

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Abstract

LVDS (Low-Voltage Differential Signals) is one of the mainstream techniques for SerDes (serializer/deserializer) I/Os. This paper presents the design and implementation of a LVDS receiver for 8B/10B SerDes. The receiver is fully compatible with IEEE Std 1596.3-1996 standard, and supports input common-mode range of 0.05 V to 2.35 V and minimum input differential signal of 100 mV. It can operate at up to 1.6 Gb/s over at least 40-inch FR4 stripline with equalization and has only 3 mW power consumption. The design is based on 0.18 μm 1.8 V/3.3 V CMOS technology using both thick (3.3 V) and thin (1.8 V) gate oxide devices.

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What this paper is about

LVDS (Low-Voltage Differential Signals) is one of the mainstream techniques for SerDes (serializer/deserializer) I/Os. This paper presents the design and implementation of a LVDS receiver for 8B/10B SerDes. The receiver is fully compatible with IEEE Std 1596.3-1996 standard, and supports input common-mode range of 0.05 V to 2.35 V and minimum input differential signal of 100 mV. It can operate at up to 1.6 Gb/s over at least 40-inch FR4 stripline with equalization and has only 3 mW power consumption. The design is based on 0.18 μm 1.8 V/3.3 V CMOS technology using both thick (3.3 V) and thin (1.8 V) gate oxide devices.

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Available abstract

LVDS (Low-Voltage Differential Signals) is one of the mainstream techniques for SerDes (serializer/deserializer) I/Os. This paper presents the design and implementation of a LVDS receiver for 8B/10B SerDes. The receiver is fully compatible with IEEE Std 1596.3-1996 standard, and supports input common-mode range of 0.05 V to 2.35 V and minimum input differential signal of 100 mV. It can operate at up to 1.6 Gb/s over at least 40-inch FR4 stripline with equalization and has only 3 mW power consumption. The design is based on 0.18 μm 1.8 V/3.3 V CMOS technology using both thick (3.3 V) and thin (1.8 V) gate oxide devices.

Key concepts: SerDes, CMOS, Equalization (audio), Electrical engineering, Electronic engineering, SIGNAL (programming language), Power consumption, Power (physics)

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