Low-power LVDS receiver for 1.3Gbps physical layer (PHY) interface

This paper presents the design of a low voltage differential signaling (LVDS) receiver for a 1.3 Gb/s physical layer (PRY) interface. The receiver supports a wide input common mode range of 0.05 V to 2.35 V and a minimum input differential signal of 100 mV as specified by the IEEE LVDS standard. The design is implemented in 0.13 /spl mu/m CMOS technology using both thick (3.3 V) and thin (1.2 V) gate oxide devices and the receiver consumes 11 mW of power. The receiver provides the interface between PHY and media access control (MAC) sub-layers.