A High-Performance CMOS LVDS Receiver

A high-performance LVDS receiver was presented,which was fully compatible with IEEE Std 1596.3-1996[1].The receiver effectively overcome the problem of low power operation and supports wide input common-mode range from 0.05 V to 2.35 V as specified by the standard.Based on HJTC's 0.18 μm 1.8 V/3.3 V logic CMOS process using both thick(3.3 V) and thin(1.8 V) gate oxide transistors,the circuit achieved a transmission rate up to 1.6 Gb/s,with an average power consumption of 1.18 mW.