Design of LVDS Interface for Gb/s Operation

This paper presents the design and the implementation of 1 Gb/s LVDS I/O interface in standard CMOS technology.By using an internal temperature independent current source and an integrated terminal resistor,the variation of LVDS signal amplitude caused by process deviation and temperature variation can be reduced 50%.The preamplifier of the receiver implements folded-cascode architecture,accompaned with an input common mode voltage detecting circuit.Thus,the input common mode voltage measurement range can satisfy the LVDS std.[1] without using low threshold transistors.And the gain of the preamplifier keeps constant independent of the common mode voltage variations,which minimized the introduced jitter when the proposed transceiver works as a buffer.The test chip occupies 0.175 mm2 and exhibits a power consumption of 33 mW with 3.3 V supply voltage.Test indicates that the transceiver can operate up to 1 Gb/s.