Implementation of CRC Encoder and Decoder Based on FPGA

The Cyclic Redundancy Check(CRC)is a widely used error control method in communicating fields to improve the reliability for data transmission.This paper introduces the principle of CRC code and the ideas on designing CRC encoder and decoder.After designing and simulating the CRC(7,3)with VHDL language on Quartus Ⅱ,the programming data files are downloaded to implement the design of CRC(7,3)encoder and decoder with FPGA chip at the last.The simulation and experiment results show that using this method the CRC encoder and decoder with fast speed,high reliability and easy large scale integration advantages are achieved.