Implementation of CRC Based on FPGA

In data communications,a high efficient error control method is needed to decrease the rate of error codes through transmission lines.CRC(Cyclic Redundancy Check)is a widely used channel coding method for its simple coding and high efficiency.The theory,algorithm and check regulations of CRC are introduced.Taking CRC4 as an example,the computation procedure and flow chart in VHDL of CRC are given.In the VHDL program,the computation is serial shift.QuartusII,an EDA tool developed by the Altera Company is used as the compilation and simulation platform.An EP1C6T144C6 belong to Cyclone is chosen to finish the FPGA realization.The realization speed is as high as 397 MHz.