2008•Unpublished venueRequires access

Design and Implementation of Reed-solomom Decoder Based on FPGA

Chao Zheng

Abstract

This paper presents an implementation of RS(255,207) decoder for DRM_DCP protocol,which is designed based on the Modified Berlekamp_Massey algorithm.The proposed circuit is capable of correcting up to 24 errors in every frame.This design use a hierarchical design/verification flow for digital signal processing IP which can effectively prompt the design efficiency.

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Available abstract

Key concepts: Computer science, Field-programmable gate array, Frame (networking), Design flow, Computer hardware, Embedded system, Protocol (science), Digital signal processing