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An implementation for shortened Reed-Solomon decoder on FPGA

Wei He

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Abstract

This paper discusses an algorithm for RS decoder, especially an improved BM(berlekamp-massey) method for the KE (key equation) solution is introduced,which can simplify the decoding process to a great extent. Based on this algorithm,the paper presents an architecture for its implementation on FPGA,in which parallel structures are largely used in order to achieve the speed as high as possible.

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What this paper is about

This paper discusses an algorithm for RS decoder, especially an improved BM(berlekamp-massey) method for the KE (key equation) solution is introduced,which can simplify the decoding process to a great extent. Based on this algorithm,the paper presents an architecture for its implementation on FPGA,in which parallel structures are largely used in order to achieve the speed as high as possible.

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Available abstract

This paper discusses an algorithm for RS decoder, especially an improved BM(berlekamp-massey) method for the KE (key equation) solution is introduced,which can simplify the decoding process to a great extent. Based on this algorithm,the paper presents an architecture for its implementation on FPGA,in which parallel structures are largely used in order to achieve the speed as high as possible.

Key concepts: Computer science, Field-programmable gate array, Decoding methods, Key (lock), Soft-decision decoder, Process (computing), Architecture, Algorithm

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