Design and implementation of fast RS encoder and decoder based on FPGA

In this paper,the design of RS(255,191) encoder and decoder is mainly introduced.According to top-down design flow FPGA implementation of this algorithm is given.The multiplier in GF(28) was realized by different ways according to their different characteristics.The encoder is designed using parallel structure,the decoder is designed using parallel-inversionless BM algorithm to implement its key module,a look-up table method is adopted to implement inversion.Using a combination of the above methods the paper enhanced the encoding and decoding speeds as maximum as possible under the permission of resources occupancy.