Implementation of Digital phase-locked Bit Synchronous extract based on VHDL

This article has designed one kind of digital phase-locked bit synchronous extraction project in the digital communication system, introduced bit synchronous extraction principles and VHDL language realization of each composition function module in detail, and have passed the simulating in the development platform -Quartus II. This design is achieved in a FPGA chip using VHDL lan-guage to program. It has the merits of good transplant、small size、low-power consumption、high reliability、facilitate to maintain and upgrade, and so on… enhanced the reliability and stability of digital communication system. This design can complete bit syn-chronous clock extraction rapidly and good stability after confirmation.