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Design and FPGA Implementation of RS(255,223) Encoder and Decoder

Xingzhao Liu

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Abstract

In this paper, the design of RS(255,223) encoder and decoder is introduced, which use multiplier in GF(28) with different structures according to their different characteristics. The encoder is designed using polynomial division and parallel structure; the decoder is designed using Euclid Algorithm, and its key module adopts series-parallel combination structure. FPGA implementation of this algorithm is given. According to top-to-down design flow, the encoder and decoder described in this paper decrease the resource usage furthest at an acceptable speed.

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What this paper is about

In this paper, the design of RS(255,223) encoder and decoder is introduced, which use multiplier in GF(28) with different structures according to their different characteristics. The encoder is designed using polynomial division and parallel structure; the decoder is designed using Euclid Algorithm, and its key module adopts series-parallel combination structure. FPGA implementation of this algorithm is given. According to top-to-down design flow, the encoder and decoder described in this paper decrease the resource usage furthest at an acceptable speed.

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Available abstract

In this paper, the design of RS(255,223) encoder and decoder is introduced, which use multiplier in GF(28) with different structures according to their different characteristics. The encoder is designed using polynomial division and parallel structure; the decoder is designed using Euclid Algorithm, and its key module adopts series-parallel combination structure. FPGA implementation of this algorithm is given. According to top-to-down design flow, the encoder and decoder described in this paper decrease the resource usage furthest at an acceptable speed.

Key concepts: Computer science, Encoder, Field-programmable gate array, Key (lock), Computer hardware, Soft-decision decoder, Design flow, Algorithm

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