Gallium arsenide dynamic random access memory support circuitry

This thesis presents the design and layout of a Gallium Arsenide (GaAs) Dynamic Random Access Memory (DRAM array of eight four-bit words including refresh circuitry. In the last several years, there has been significant research investigating the possibilities of producing much faster, lower power and high density DRAM using GaAs. Thus far, this research has yielded success on a limited basis using special materials and fabrication techniques. This design, tested and simulated using HSPICE, supports a memory access time of approximately three nanoseconds, faster than present commercial Static Random Access Memory (SRAM). The logic circuits are designed using GaAs enhancement-mode and depletion-mode (E/ D) metal semiconductor field-effect transistors (MESFETs). Charge storage is facilitated by a single GaAs MESFET connected to a parallel plate capacitor and the required minimum time between refresh is approximately three milliseconds. Power consumption is acceptable and fabrication by Vitesse Semiconductor Corporation using the HGaAs3 process is in progress. The design techniques, power consumption and timing are discussed and demonstrated for the basic logic circuits and the memory array read, write and refresh cycles. A significant increase in DRAM memory bandwidth is gained narrowing the memory bandwidth differential between primary memory and the processor.