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2003•10th Annual IEEE (GaAs IC) Symposium, Gallium Arsenide Integrated Circuit. Technical Digest 1988.Requires access

A 3 ns 1 K*4 static self-time GaAs RAM

A. Fiedler, Jae Wook Chun, D. Kang

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Abstract

A GaAs 1 K*4 static self-timed random-access memory (SSTRAM) with input and output latches and internal write-pulse generation has been designed, fabricated, and tested. Fully functional SSTRAMs have been obtained, with a worst-case clock access time (equal to read and write cycle time) of 3.6 ns for a 1.9-W device. This part is manufactured using three levels of interconnect metallization and a novel high-margin enhancement-depletion (HMED) process, and utilizes many innovative circuits. >

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What this paper is about

A GaAs 1 K*4 static self-timed random-access memory (SSTRAM) with input and output latches and internal write-pulse generation has been designed, fabricated, and tested. Fully functional SSTRAMs have been obtained, with a worst-case clock access time (equal to read and write cycle time) of 3.6 ns for a 1.9-W device. This part is manufactured using three levels of interconnect metallization and a novel high-margin enhancement-depletion (HMED) process, and utilizes many innovative circuits. >

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Available abstract

A GaAs 1 K*4 static self-timed random-access memory (SSTRAM) with input and output latches and internal write-pulse generation has been designed, fabricated, and tested. Fully functional SSTRAMs have been obtained, with a worst-case clock access time (equal to read and write cycle time) of 3.6 ns for a 1.9-W device. This part is manufactured using three levels of interconnect metallization and a novel high-margin enhancement-depletion (HMED) process, and utilizes many innovative circuits. >

Key concepts: Access time, Computer science, Electronic circuit, Interconnection, Process (computing), Optoelectronics, Parallel computing, Materials science

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