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Subnanosecond 8 Bit Normally-Off GaAs SRAM

Pierrette Frey, Bertrand Gabillard, Marc Rocchi

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Abstract

This paper presents the design and fabrication of the first subnanosecond 8 bit - Normally-off GaAs SRAM ever reported. The fabrication process based on 0.9 ?m long recessed gate MESFET's utilises only one active layer. Its simplicity makes it easily adaptable to much higher density circuits. The 8 bit - SRAM has yielded an access time of 0.9 ns for a corresponding power consumption (output buffer excluded) of 6.5 mW.

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What this paper is about

This paper presents the design and fabrication of the first subnanosecond 8 bit - Normally-off GaAs SRAM ever reported. The fabrication process based on 0.9 ?m long recessed gate MESFET's utilises only one active layer. Its simplicity makes it easily adaptable to much higher density circuits. The 8 bit - SRAM has yielded an access time of 0.9 ns for a corresponding power consumption (output buffer excluded) of 6.5 mW.

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Available abstract

This paper presents the design and fabrication of the first subnanosecond 8 bit - Normally-off GaAs SRAM ever reported. The fabrication process based on 0.9 ?m long recessed gate MESFET's utilises only one active layer. Its simplicity makes it easily adaptable to much higher density circuits. The 8 bit - SRAM has yielded an access time of 0.9 ns for a corresponding power consumption (output buffer excluded) of 6.5 mW.

Key concepts: MESFET, Static random-access memory, Fabrication, Electronic circuit, Bit (key), Electronic engineering, Power consumption, Logic gate

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