Gallium arsenide DRAM memory cell design and evaluation of test methods

This thesis proposes a new Gallium Arsenide (GaAs) Dynamic Random Access Memory (DRAM) storage cell design based on an n-type, depletion mode diode and evaluates an Emitter-Coupled Logic (ECL) based test platform. The depletion mode diode storage cell exhibits improved charge storage and maintenance characteristics when compared with a previously designed capacitor- based storage cell. Power requirements of the diode-based cell are marginally increased. The modularity of the new diode-based design produces impressive improvements in Very Large Scale Integration (VLSI) layout. The smaller design promises a higher degree of memory cell integration for future GaAs DRAM applications. The ECL test platform provides DATA, READ, WRITE, REFRESH and CLOCK signals as well as power and ground requirements for a GaAs DRAM chip in a 132-pin package. All testbench systems are tested and prove functional but CLOCK and REFRESH signal integrity suffer from noise and connector losses above 100 MHz. Ultimately, the ECL test platform failed to test the existing GaAs DRAM due to pin-out incompatibility. Recommendations for future test platforms are discussed along with suggestions for incorporation of the diode-based memory cell in new DRAM designs. jg p2