A low leakage 500MHz 2T embedded dynamic memory with integrated semi-transparent refresh

This paper presents a low-leakage 128 kbit dynamic memory based on a 2T dynamic cell. The design is implemented in a logic 90 nm technology and achieves a low static power consumption of 130 μW and an access time of 2 ns. It has a worst case retention time of 175 μs. This performance is achieved by introducing an optimized hierarchical organization and peripheral circuits for the read, the write and the refresh operations. A novel writing mechanism for 2T cells using a two phases approach is demonstrated. The area penalty of using short read bitlines is alleviated using a charge transfer sense amplifier. A novel local write sense amplifier that can operate as a latch makes it possible to perform the refresh operation at the local level, improving the energy efficiency of the refresh operation. The memory includes an integrated automatic refresh mechanism. During refresh cycles, most read and write operations can still be performed. In cases where the address conflicts with the refresh operation, the memory handles access recovery internally.