A new extension method of retention time for memory cell on dynamic random access memory

Demands have been placed on a dynamic random access memory (DRAM) to not only have increased memory capacity and data transfer speed but also have reduced operating and standby currents. When a system uses a DRAM, a refresh operation is necessary because of its data retention time restriction: each bit of the DRAM is stored as an amount of electrical charge in a storage capacitor. Power consumption for the refresh operation increases in proportion to the memory capacity. A new method is proposed to reduce refresh power consumption dynamically when the full memory capacity is not required, by effectively extending the memory cell retention time. Conversion from 1 cell/bit to 2N cells/bit reduces the variation of retention time among memory cells. This method reduces the frequency of disturbance and its power consumption by two orders of magnitude. The conversion itself can be realized very simply from the structure of the DRAM array circuit, maintaining all conventional functions and operations in case of the full array access mode.