2010Unpublished venueRequires access

Evolutionary development of Wafer Level Packaging

John Hunt

Open publisher page 1 citations

Abstract

IBM created the wafer processing technology and concepts more than 45 years ago that would later enable what we call Wafer Level Packaging. With its introduction of the Controlled Collapse Chip Connect (C4) solder bumping process for use in its Solid Logic Technology package, it paved the way for the larger solder bump technology that enabled die to be mounted directly on circuit boards using standard surface mount equipment, and standard pitch circuit board technologies. Over ten years ago, Wafer Level Chip Scale Packaging (WLCSP) came into volume production, with all of the “packaging” done while still in wafer form. It began slowly, with very small packages having solderball counts of 2-6 I/Os. Over the years, the production volumes have grown, and so has the I/O count. Much of the industry still perceives WLCSPs as limited to low I/O count simple applications. However, within the last few years, there have been growing demands for WLCSP packages with I/O counts of 300 and greater, and with higher levels of complexity.

About this research paper

What this paper is about

IBM created the wafer processing technology and concepts more than 45 years ago that would later enable what we call Wafer Level Packaging. With its introduction of the Controlled Collapse Chip Connect (C4) solder bumping process for use in its Solid Logic Technology package, it paved the way for the larger solder bump technology that enabled die to be mounted directly on circuit boards using standard surface mount equipment, and standard pitch circuit board technologies. Over ten years ago, Wafer Level Chip Scale Packaging (WLCSP) came into volume production, with all of the “packaging” done while still in wafer form. It began slowly, with very small packages having solderball counts of 2-6 I/Os. Over the years, the production volumes have grown, and so has the I/O count. Much of the industry still perceives WLCSPs as limited to low I/O count simple applications. However, within the last few years, there have been growing demands for WLCSP packages with I/O counts of 300 and greater, and with higher levels of complexity.

Why it matters

OpenAlex reports 1 citations for this work. Citation counts describe recorded attention and do not establish research quality.

Key contribution

A contribution statement is not available in the OpenAlex record.

Method / approach

Method details are not available in the OpenAlex metadata.

Main findings

Findings are not separately available in the OpenAlex metadata.

Limitations

Limitations are not available in the OpenAlex metadata.

Applications

Application details are not available in the OpenAlex metadata.

Available abstract

IBM created the wafer processing technology and concepts more than 45 years ago that would later enable what we call Wafer Level Packaging. With its introduction of the Controlled Collapse Chip Connect (C4) solder bumping process for use in its Solid Logic Technology package, it paved the way for the larger solder bump technology that enabled die to be mounted directly on circuit boards using standard surface mount equipment, and standard pitch circuit board technologies. Over ten years ago, Wafer Level Chip Scale Packaging (WLCSP) came into volume production, with all of the “packaging” done while still in wafer form. It began slowly, with very small packages having solderball counts of 2-6 I/Os. Over the years, the production volumes have grown, and so has the I/O count. Much of the industry still perceives WLCSPs as limited to low I/O count simple applications. However, within the last few years, there have been growing demands for WLCSP packages with I/O counts of 300 and greater, and with higher levels of complexity.

Key concepts: Wafer, Wafer-level packaging, Wafer-scale integration, Computer science, Materials science, Optoelectronics

Related papers

Back to paper searchBrowse research topicsOriginal source
Evolutionary development of Wafer Level Packaging — Research Paper | ScholarLens