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2005•Unpublished venueOpen access

Wafer-level chip-scale packaging for low-end RF products

M. Bartek, G. Zilber, D. Teomin, A. Polyakov, S.M. Sinaga, P. M. Mendes, Joachim N. Burghartz

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Abstract

The paper gives a short overview of wafer-level chip-scale packaging technology and analyses its added value in the packaging of RF ICs. Particularly, the possibilities of substrate crosstalk suppression by substrate thinning and trenching together with embedding of RF passives (inductors, antennas) are addressed. The Shellcase-type wafer-level packaging solution is used as a study case presenting its fabrication aspects and its potential for RF IC packaging.

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What this paper is about

The paper gives a short overview of wafer-level chip-scale packaging technology and analyses its added value in the packaging of RF ICs. Particularly, the possibilities of substrate crosstalk suppression by substrate thinning and trenching together with embedding of RF passives (inductors, antennas) are addressed. The Shellcase-type wafer-level packaging solution is used as a study case presenting its fabrication aspects and its potential for RF IC packaging.

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OpenAlex reports 2 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

The paper gives a short overview of wafer-level chip-scale packaging technology and analyses its added value in the packaging of RF ICs. Particularly, the possibilities of substrate crosstalk suppression by substrate thinning and trenching together with embedding of RF passives (inductors, antennas) are addressed. The Shellcase-type wafer-level packaging solution is used as a study case presenting its fabrication aspects and its potential for RF IC packaging.

Key concepts: Wafer-level packaging, Wafer-scale integration, Chip-scale package, Wafer, Packaging engineering, Integrated circuit packaging, Embedding, Materials science

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