2006Unpublished venueRequires access

RF-MEMS wafer-level packaging using through-wafer via technology

J. Tian, Jacopo Iannacci, S. Sosin, R. Gaddi, M. Bartek

Open publisher page 16 citations

Abstract

This paper presents wafer-level packaging (WLP) solution for RF-MEMS applications based on through-wafer via (TWV) technology in high-resistivity silicon (HRS). A pre-processed HRS capping wafer containing recesses and vertical Cu-plated TWV interconnect is, after alignment, bonded to the RF-MEMS wafer providing environmental protection and easy signal access. Optionally, cavities can be formed simultaneously with TWV in the capping wafer, which allows hybrid co-integration of additional IC dies while maintaining overall thickness of the resulting SMT compatible package. This cavity can also be used for a first-level wafer-to-wafer alignment accuracy check. After bonding, the s-parameter measurement at giga hertz level shows little influence introduced by the capping substrate.

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What this paper is about

This paper presents wafer-level packaging (WLP) solution for RF-MEMS applications based on through-wafer via (TWV) technology in high-resistivity silicon (HRS). A pre-processed HRS capping wafer containing recesses and vertical Cu-plated TWV interconnect is, after alignment, bonded to the RF-MEMS wafer providing environmental protection and easy signal access. Optionally, cavities can be formed simultaneously with TWV in the capping wafer, which allows hybrid co-integration of additional IC dies while maintaining overall thickness of the resulting SMT compatible package. This cavity can also be used for a first-level wafer-to-wafer alignment accuracy check. After bonding, the s-parameter measurement at giga hertz level shows little influence introduced by the capping substrate.

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Available abstract

This paper presents wafer-level packaging (WLP) solution for RF-MEMS applications based on through-wafer via (TWV) technology in high-resistivity silicon (HRS). A pre-processed HRS capping wafer containing recesses and vertical Cu-plated TWV interconnect is, after alignment, bonded to the RF-MEMS wafer providing environmental protection and easy signal access. Optionally, cavities can be formed simultaneously with TWV in the capping wafer, which allows hybrid co-integration of additional IC dies while maintaining overall thickness of the resulting SMT compatible package. This cavity can also be used for a first-level wafer-to-wafer alignment accuracy check. After bonding, the s-parameter measurement at giga hertz level shows little influence introduced by the capping substrate.

Key concepts: Wafer, Wafer-level packaging, Wafer testing, Microelectromechanical systems, Materials science, Wafer backgrinding, Optoelectronics, Die preparation

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